Embodiments disclosed herein relate to computer hardware. More specifically, embodiments disclosed herein relate to bandwidth limiting on generated PCIe packets from a debug source.
Computer systems often use multiple computers that are coupled together in a common chassis. The computers may be separate servers that are coupled by a common backbone within the chassis. Each server is a pluggable board that includes at least one processor, an on-board memory, and an Input/Output (I/O) interface. Further, the servers may be connected to a switch to expand the capabilities of the servers. For example, the switch may permit the servers to access additional Ethernet networks or PCIe slots, as well as permit communication between servers in the same or different chassis.
A PCI Express bus is an implementation of the Peripheral Components Interconnect (‘PCI’) computer bus according to the set of PCI Express specifications promulgated by the PCI Special Interest Group (‘PCI SIG’). A PCI Express bus uses existing PCI programming and software concepts, but is based on a different and much faster serial physical-layer communications protocol. The physical-layer consists not of a bus, but of a network of serial interconnections extending to each device from a switch. The switch provides point-to-point communications between devices connected to the switch. Devices and switches operating according to the PCI Express specifications are generally referred to as ‘PCI Express devices’ and ‘PCI Express switches’ respectively.
A connection between any two PCI Express devices is referred to as a ‘link.’ A link consists of a collection of one or more lanes used for data communications between devices. Each lane is a set of two unidirectional low voltage differential signaling pairs of transmission pathways such as, for example, traces along a motherboard. Because transmitting data and receiving data are implemented using separate differential pairs, each lane allows for full-duplex serial data communication of up to eight gigabits of data per second.